1. Field of the Invention
The present invention is directed generally to a method for manufacturing a multilayer gate electrode containing doped polysilicon and metal silicide in a MOS transistor.
2. Description of the Related Art
In CMOS technology, simultaneous silicidation of gate regions and source/drain regions is gaining in significance. The reduction in sheet resistivity and contact resistance of the gate electrode, as well of the source/drain terminals, that is thereby achieved contributes to an improvement in transistor performance. This method is referred to as the SALICIDE process (or self aligned silicide) and is known, for example form a publication by M.E. Alperin et al., "Development of the Self-Aligned Titanium Silicide Process for VLSI Applications", IEEE Transactions on Electron Devices, Vol. ED-32, no. 2, p. 141-149 (1985). According to this reference, a metal, such as titanium, is deposited surface-wide on the surface of the source or the drain regions, as well as onto a doped polysilicon structure that is arranged above the gate oxide and that forms part of the gate electrode. When subject to designational tempering, a formation of silicide occurs on the exposed silicon surfaces; in other words, on the doped polysilicon structure as well as on the surface of the source/drain regions. By contrast, unreacted metal is preserved on the surfaces that are masked with an oxide or a nitride. The metal and the potential reaction products are removed with an etchant that selectively removes only the metal relative to the silicide. Thus, only the silicidated gate electrode and source/drain terminals remain.
A significant disadvantage of this method is that a dopant depletion occurs during the tempering process. In this context, dopant depletion refers to a flow-back of dopant out of the silicon regions into the silicide. This effect is especially pronounced in the doped polysilicon structure due to the rapid grain boundary diffusion.
The reason for the dopant depletion is that parasitic metal-to-dopant reactions occur simultaneously with the formation of the metal silicide. Stable metal-dopant compounds, such as TiB.sub.2, are formed in this metal-to-dopant reaction.
When the dopant concentration in the doped polysilicon which forms part of the gate electrode falls below approximately 5.times.10.sup.-19 cm.sup.-3, in other words, when the doped polysilicon structure no longer contains degenerated doped polysilicon, then a space charge zone is formed in the gate electrode. This effect is referred to as gate depletion and is known, for example, from the publication by C.Y. Wong et al., "Doping of N.sup.+ and P.sup.+ Polysilicon in a Dual-Gate CMOS Process", Technical Digest IEDM 88, pages 238 through 241 (1988).
In an article by R.A. Chapman et al., "0.5 Micron CMOS for High Performance at 3.3 V", Technical Digest IEDM 88, pages 52 through 55 (1988), it is known that the dopant depletion in the doped polysilicon structure causes a reduction of the saturation drain current. It also deteriorates the below threshold behavior.
The dopant depletion also leads to changes in the electron affinity and, thus, to shifts in the cutoff voltage.
In the publication by H. Hayashida et al., "Dopant Redistribution in Dual Gate W-Polycide CMOS and its Improvement by RTA", Conference Proceedings VLSI Symposium, pages 29-30 (1989) and in a publication by B. Davari et al., "A High Performance 0.25 .mu.m CMOS Technology", Technical Digest IEDM 88, Pages 56-59 (1988) is disclosed measures which attempt to suppress the dopant depletion.
In the foregoing Hayashida et al. reference, it is disclosed that the dopant depletion can be influenced by a limitation of the annealing temperature budget. The reduction of the temperature budget, however, means a significant limitation in the process management. Only slight improvements with respect to the dopant depletion can be achieved with this measure, so that the limitation of the process management involved here does not seem justifiable.
In the D. Davari et al. reference cited above is disclosed that the dopant depletion may be influenced by a reduction of the silicide thickness. A reduction in the silicide thickness, however, leads to reduction in the conductivity of the gate electrode. Over and above this, the temperature stability of this silicide is also deteriorated (see further the publication by R. Burmester et al., "Reduction of Titanium Silicide Degradation During Borophosphosilicate Glass Reflow", Conference Proceedings ESSDERC 89, pages 233-236 (Springer Verlag, 1989, edited by Heuberger, Ryssel, Lange)).